Open - FPGA CoE

OBJECTIVES

Primary objectives of CoE are , but not limited to:

• Create HW and SW infrastructure to enable development and verification of custom RISC V CPU.
• Create RISC-V Cores based evaluation HW for use in LoRaWAN Applications.
• Promote Open Source Hardware at Silicon Level.

Drive the adoption of Open Hardware among startups.

FPGA Lab
Hardware :

• Evaluation HW from Olimex,MCCI etc based on Lattice ICE FPGA's .
  
• Industrial boards such as Digilient Arty A7 100 T
• Test Bench Equipment.
  
  Software:

• Software tools for PNR Synthesis
• Tools for Verilog development workflow
• Tools for verification( Pre-Silicon).